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DS28CZ04: 4Kb I2C/SMBus EEPROM with Nonvolatile PIO
mode and generate pulses on SCL to read data, one byte after another without issuing a STOP (see Table 2B).
Eventually the BUSY bit changes from 1 to 0 indicating the end of the write cycle. The BUSY bit is sampled during
the transmission of the byte before it is read out; consequently, the state read out reflects the state at sample
time and not the actual state. To get the actual state of the busy bit the master can a) read at the maximum data
rate, b) read two bytes in sequence without delay in between and use the BUSY bit in the second byte or c) in a
loop: read one byte, issue a STOP, wait, reposition the read pointer, address the DS28CZ04 in read mode to get
another status byte.
Table 1B. Prepare For Busy Polling
WRITING WHILE DEVICE IS BUSY
PIO Mode
Starting Address
SMBus Mode
I2C Bus Mode
Slave address is acknowledged;
Either
Address
Mode
Device Address = A0h,
memory address = 7Ah
Device Address = A0h,
any memory address
except 7Ah
Device Address = A2h,
any memory address
memory address is acknowl-
edged; data is not acknowledged;
write pointer keeps its last posi-
tion; read pointer = 7Ah .
Slave address is acknowledged;
memory address is not acknowl-
edged; data is not acknowledged;
write pointer keeps its last posi-
tion; read pointer = write pointer
+1.
Slave address is NOT ac-
knowledged; memory ad-
dress is not acknowledged;
data is not acknowledged;
write pointer keeps its last
position; read pointer = write
pointer +1.
Table 2B. Busy Polling
READING WHILE DEVICE IS BUSY
PIO Mode
Either
Address
Mode
Read Pointer
Device Address = A0h ,
memory address = 7Ah
Device Address = A0h ,
excluding memory
address 7Ah
Device Address = A2h ,
SMBus Mode
Slave address is acknowledged;
data is delivered;
read pointer stays at 7Ah .
Slave address is acknowledged;
no data is delivered; read pointer
= last write pointer +1.
I2C Bus Mode
Slave address is NOT
acknowledged;
no data is delivered;
read pointer stays as is.
any memory address
Writing to SRAM and PIO Locations
If the DS28CZ04 is addressed in write access mode, any data bytes that follow the address are directly written to
their respective memory location. The PIO address mode controls the device behavior when writing to the PIO
Read/Write access registers. Depending on whether one runs into the PIO address range (SRAM write) or whether
one starts at a PIO address (PIO direct) the pointer and data acknowledge behavior is different. Table 1A shows
the details. The PIO Address Mode is another parameter that affects the pointer behavior. Figure 7 illustrates the
possible cases and the sequence in which the addresses are accessed.
The common characteristic in both SRAM write cases is a starting address in the SRAM block (address range 78h
to 7Fh) excluding any address used for PIO access . Data for writeable registers (7Ah, 7Bh and valid addresses
for PIO Read/Write access) is acknowledged; the write pointer increments and after address 7Fh rolls over to 7Ah.
The common characteristic in both PIO direct cases is a starting address within the address range used for PIO
access . In PIO Multi-Address Mode, there are four such addresses (7Ch to 7Fh); each PIO occupies its own
address. Data is always acknowledged; the write pointer increments to the next PIO and eventually wraps around
to 7Ch. In PIO Single-Address Mode, there is exactly one address (7Ch) that is shared by all PIOs. Data is always
acknowledged; the write pointer stays at 7Ch.
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